To understand the invention, it is necessary to appreciate the nature of three types of errors that occur in operation of mass storage devices, such as disk and tape drive memory systems. For specificity, much of the following discussion will refer to magnetic disk drive systems. However, it will be apparent that the discussion may readily be generalized to apply to the operation of other mass storage devices such as optical disk drive systems and magnetic tape drive systems.
FIG. 1 is a block diagram of a conventional magnetic disk drive system. Disk 1 includes a number of concentric tracks such as track 2. Magnetic read/write head 3 is separated by a small distance (typically about 0.00001 inches) from track 2, so that head 3 can read data from track 2 as disk 1 rotates relative to head 3. The analog signal read by head 3 is amplified in read pre-amplifier 4 and supplied to pulse peak detector 5. Pulse detector 5 differentiates the analog signal, and generates a digital signal whose pulses have leading edges corresponding to the zero-crossing points of the differentiated analog signal which correspond to the peaks and troughs of the incoming analog signal. Alternatively, unit 5 may be any circuit which generates a digital signal whose leading edges correspond to the peaks and troughs of the incoming signal.
The digital signal emerging from unit 5 is then synchronized with a phase-locked VCO clock signal in synchronizer 7 to eliminate jitter, and is supplied to decoder 8 where it is converted to serial NRZ format suitable for processing in controller 9.
NRZ digital data to be written on disk 1 by head 3 is encoded into a desired format such as the well-known 2,7 RLL (Run Length Limited) code format in encoder unit 10. In 2,7 RLL code, each bit representing a "one" is preceded and followed by a minimum of two zeros and a maximum of seven zeros. The encoded data then undergoes precompensation in circuit 6 and is supplied to write driver 11, which generates appropriate signals to cause drive head 3 to write the data on disk 1. Selection element 12 performs the function of selecting one of the read/write heads (in an embodiment including two or more independently selectable heads), selecting either a Read or Write mode, and (in the Write mode) supplying the proper write current to the head selected to write data onto disk 1.
Precompensation circuit 6 compensates for bit shift due to the tendency of closely spaced pulses to "repel" one another. This tendency causes two pulses written with minimum separation to be read back with more than one half the separation of two bits written with twice the minimum separation. Circuit 6 detects patterns (in the digital signal emerging from encoder 10) likely to exhibit such pattern-sensitive bit shifting. Then, while delaying the bits not selected by a nominal amount, circuit 6 delays the selected bits by more than a nominal amount (i.e., those selected bits likely to be "Early") or by less than a nominal amount (i.e., those selected bits likely to be "Late").
The above mentioned pattern sensitivity phenomenon (the repulsion between adjacent bits) is a significant source of error in reading from and writing onto a mass storage device (such as a disk or tape drive memory system). The phenomenon is most pronounced at highest recorded bit densities, and accordingly varies in magnitude from track to track on a disk, having maximum magnitude for the track having minimum radius. The phenomenon also varies with other parameters such as head variations, media variations, and head to media spacing. Thus, it is desirable to perform precompensation and precompensation recalibration for each disk drive read/write head, or each disk surface, or both.
However, there are two other significant sources of error in reading from and writing onto a mass storage device, namely window centering error and pulse pairing error. It is possible to define a parameter representing the contribution of each of pattern sensitivity error, window centering error, and pulse pairing error to the overall system error rate.
Window centering error is most readily characterized by the averaged time difference between the leading edge of each data pulse entering synchronizer 7 and the leading edge of each phase-locked VCO clock pulse. The leading edge of the data pulses will ideally be positioned in time at the exact center of a time "window" defined by adjacent clock pulse leading edges. The data will be strobed out (as "Sync Data") by the "Clock" leading edge following the "Data" leading edge. Positioning the average "Data" leading edge at the exact center of the "window" allows any specific data pulse to be shifted forward or back by up to one half the window period and still be strobed out by the proper (next) clock pulse. Increasing the average time separation between the clock edges and the data pulse centers will decrease the overall system error rate. Typically, the "window center" can be adjusted by varying the relative delays of the Data pulse leading edges and the clock pulse leading edges. Window centering error is purely a function of the accuracy of the Data and Clock relative delays in the synchronizer, and accordingly the operation of window centering need only be performed once for each drive employing multiple heads (not once for each read/write head).
Synchronizer 7 of the FIG. 1 system includes delay circuit 7a for shifting the phase of the phase-locked VCO clock pulses generated therein relative to the received Data pulse leading edges. It is conventional for the phase shift produced by delay circuit 7a to be variable in response to control signals supplied from controller 9 on line C.sub.1. Thus, the contribution of window centering error to the overall system error rate may be varied by such control signals on line C.sub.1.
Pulse pairing error results from the asymmetry between positive and negative flux transitions, which may be induced anywhere in the write-channel and read-channel circuitry. FIG. 2 shows one way in which pulse pairing may arise. Signal (a) has form typical of the amplified output of a magnetic disk drive read/write head, and includes positive polarity pulses 20, 22, and 24 alternating with negative polarity pulses 21, 23, and 25. Magnets 13-17 comprise part of a sector of track 2 of disk 1 in FIG. 1. Each track of disk 1 includes a plurality of independent sectors. When read/write head 3 is passing over the intersection of magnets 14 and 15, a positive voltage pulse will be induced in head 3, which when amplified will be shaped as positive pulse 22. Similarly, negative pulse 23 corresponds to the signal induced when head 3 is passing over the intersection of magnets 15 and 16.
The average separation between each adjacent pulse is equal to T. Signal (a), after it is differentiated in one of the circuit elements has the waveform of signal (b). The zero-crossings of signal (b) correspond to peaks or troughs of signal (a). Signal (d) represents the ideal output of a circuit for generating a train of pulses whose leading edges align with the zero-crossings of signal (b). In practice, the actual output of such a circuit will likely resemble signal (c), which exhibits pulse pairing. Typically, a circuit intended to generate a stream of digital pulses from signal (b) will produce pulses whose leading edges align, not with zero-crossings of signal portions 30-35, but instead with points of signal (b) having a small amplitude offset as shown in FIG. 2. Thus, the pulses of signal (c) are paired, with alternating long spacing T1 and short spacing T2 between adjacent pulses. Specifically, each pair of adjacent pulses associated with a positive polarity peak followed by a negative polarity peak (i.e., pair of pulses 41 and 42) will have increased separation T1 (where T1 is greater than T) and each pair of adjacent pulses associated with a negative polarity peak followed by a positive polarity peak transition (i.e., pair of pulses 42 and 43) will have decreased separation T2 (where T2 is less than T).
It is conventional to test disk drive systems to measure their error rates (the error rate of a system is the number of bits processed incorrectly by the system divided by the number of bits processed correctly by the system). However, conventional error tests are very time-consuming, commonly requiring on the order of several hours. Such conventional tests have been timeconsuming because typical error rates for disk drive systems are extremely low (for example 10-10), so that statistically significant accumulations of errors requires that many bits of data be read (at typical data rates in the range 5-20 Megabits/sec). Further, a practical, inexpensive method and means for rapidly and independently measuring and varying the error rate for each read/write head (or each storage medium track) has not been developed. Nor has a practical means been developed for independently varying the window centering, pulse pairing, and pattern sensitivity error parameters of a mass storage device memory system.
It would be desirable to perform error measurement tests sufficiently rapidly so that mass storage device users and manufacturers could routinely perform them whenever operating the device. If the users could also rapidly minimize the system error rate in conjunction with each such test, the users could routinely optimize the data integrity of their systems. Device manufacturers could then increase the capacity of such optimizible devices (or reduce their cost without reducing capacity) because the optimizible devices would require less error margin. Because certain contributions to overall system error vary from read/write head to read/write head of a multiple head system (for example, precompensation error and pulse pairing error), it would be desirable if users and manufacturers could rapidly minimize the error rate associated with each read/write head of such a system.